ISCA87: Table of contents

Ditzel, D. R.; McLellan, H. R.: Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero. 2-9.

DeRosa, J. A.; Levy, H. M.: An Evaluation of Branch Architectures. 10-17.

Hwu, W. W.; Patt, Y. N.: Checkpoint Repair for Out-of-Order Execution Machines. 18-26.

Sohi, G. S.; Vajapeyam, S.: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 27-34.

Swensen, J.; Patt, Y.: Fast Temporary Storage for Serial and Parallel Execution. 35-45.

Wong, K.; Franklin, M. A.: Performance Analysis and Design of a Logic Simulation Machine. 46-55.

Doshi, K.; Varman, P.: A Modular Systolic Architecture for Image Convolutions. 56-63.

Fujita, S.; Aibara, R.; Yamashita, M.; Ae, T.: A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture. 64-71.

Mendelson, B.; Silberman, G. M.: Mapping Data Flow Programs on a VLSI Array of Processors. 72-80.

Ghosal, D.; Bhuyan, L. N.: Analytical Modeling and Architectural Modifications of a Dataflow Computer. 81-89.

Takesue, M.: A Unified Resource Management and Execution Control Mechanism for Data Flow Machines. 90-99.

Abe, S.; Bandon, T.; Yamaguchi, S.; Kurosawa, K.; Kiriyama, K.: High Performance Integrated Prolog Processor IPP. 100-107.

Fagin, B. S.; Despain, A. M.: Performance Studies of a Parallel Prolog Architecture. 108-116.

Civera, P. L.; Maddaleno, F.; Piccinini, G. L.; Zamboni, M.: An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. 117-127.

Ridoux, O.: Deterministic and Stochastic Modeling of Parallel Garbage Collection: Towards Real-Time Criteria. 128-136.

Sun, C.; Tsu, Y.: The Sharing of Environment in AND-OR-Parallel Execution of Logic Programs. 137-144.

Guha, A.; Ramnarayan, R.; Derstine, M.: Architectural Issues in Designing Symbolic Processors in Optics. 145-153.

Varma, A.; Raghavendra, C. S.: Rearrangeability of Multistage Shuffle/Exchange Networks. 154-162.

Beivide, R.; Herrada, E.; Balcazar, J. L.; Labarta, J.: Optimized Mesh-Connected Networks for SIMD and MIMD Architectures. 163-170.

Harper III, D. T.; Jump, J. R.: Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks. 171-177.

Ramachandran, U.; Solomon, M.; Vernon, M.: Hardware Support for Interprocess Communication. 178-188.

Dally, W. J.; Chao, L.; Chien, A.; Hassoun, S.; Horwat, W.; Kaplan, J.; Song, F.; Totty, B.; Wills, S.: Architecture of a Message-Driven Processor. 189-196.

Kumar, M.: Effect of Storage Allocation/Reclamation Methods on Parallelism and Storage Requirements. 197-207.

Chang, J. H.; Chao, H.; So, K.: Cache Design of a Sub-Micron CMOS System/370. 208-213.

Freeman, M.: An Architectural Perspective on a Memory Access Controller. 214-223.

Cheung, K.; Sohi, G.; Saluja, K.; Pradhan, D.: Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. 224-233.

Scheurich, C.; Dubois, M.: Correct Memory Operation of Cache-Based Multiprocessors. 234-243.

Wilson, J. A. W.: Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors. 244-252.

Lee, R. L.; Yew, P.-C.; Lawrie, D. H.: Multiprocessor Cache Design Considerations. 253-263.

Eickemeyer, R. J.; Patel, J. H.: Performance Evaluation of Multiple Register Sets. 264-271.

Stanley, T. J.; Wedig, R. G.: A Performance Analysis of Automatically Managed Top of Stack Buffers. 272-281.

Moore, B.; Padegs, A.; Smith, R.; Buchholz, W.: Concepts of the System/370 Vector Architecture. 282-289.

Pleszkun, A. R.; Goodman, J. R.; Hsu, W.-C.; Joersz, R. T.; Bier, G.; Woest, P.; Schechter, P. B.: WISQ: A Restartable Architecture Using Queues. 290-299.

Chow, P.; Horowitz, M.: Architectural Tradeoffs in the Design of MIPS-X. 300-308.

Ditzel, D. R.; McLellan, H. R.; Berenbaum, A. D.: The Hardware Architecture of the CRISP Microprocessor. 309-319.