ISCA88: Table of contents

Ghosh, J.; Hwang, K.: Critical Issues in Mapping Neural Networks on Message-Passing Multicomputers. 3-11.

Takefuji, Y.; Jannarone, R.; Cho, Y. B.; Chen, T.: Multinomial Conjunctoid Statistical Learning Machines. 12-17.

Louri, A.; Hwang, K.: A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution. 18-29.

Fiske, S.; Dally, W. J.: The Reconfigurable Arithmetic Processor. 30-36.

Pleszkun, A. R.; Sohi, G. S.: The Performance Potential of Multiple Functional Unit Processors. 37-44.

Hwu, W. W.; Chang, P. P.: Exploiting Parallel Microprocessor Microarchitectures with a Compiler Code Generator. 45-55.

McNiven, G. D.; Davidson, E. S.: Analysis of Memory Referencing Behavior for Design of Local Memories. 56-63.

Eickenmever, R. J.; Patel, J. H.: Performance Evaluation of On-Chip Register and Cache Organizations. 64-72.

Baer, J.-L.; Wang, W.-H.: On the Inclusion Properties for Multi-Level Cache Hierarchies. 73-80.

Short, R. T.; Levy, H. M.: A Simulation Study of Two-Level Caches. 81-89.

Chow, E.; Madan, H.; Peterson, J.; Grunwald, D.; Reed, D.: Hyperswitch Network for the Hypercube Computer. 90-99.

Winsor, D. C.; Mudge, T. N.: Analysis of Bus Hierarchies for Multiprocessors. 100-107.

Wei, S.; Lee, G.: Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network. 108-115.

Jiang, H.; Smith, K. C.: A Partial-Multiple-Bus Computer Structure with Improved Cost Effectiveness. 116-123.

Watson, I.; Woods, V.; Watson, P.; Banach, R.; Greenberg, M.; Sargeant, J.: Flagship: A Parallel Architecture for Declarative Programming. 124-130.

Iannucci, R. A.: Toward a Dataflow/von Neumann Hybrid Architecture. 131-140.

Culler, D. E.; Arvind, G.: Resource Requirements of Dataflow Programs. 141-151.

Sprunt, B.; Kirk, D.; Sha, L.: Priority-Driven, Preemptive I/O Controllers for Real-Time Systems. 152-159.

Shukla, S. B.; Agrawal, D. P.: A Kernel-Independent, Pipelined Architecture for Real-Time 2-D Convolution. 160-166.

Liu, W.; Yeh, T.-F.; Batchelor, W. E.; Cavin, R.: Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions. 167-175.

Clark, D. W.; Bannon, P. J.; Keller, J. B.: Measuring VAX 8800 Performance with a Histogram Hardware Monitor. 176-185.

Sites, R. L.; Agarwal, A.: Multiprocessor Cache Analysis Using ATUM. 186-195.

Ng, S.; Lang, D.; Selinger, R.: Tradeoffs between Devices and Paths in Achieving Disk Interleaving. 196-203.

Jainandunsing, K.; Deprettere, E. F.: Design of a Concurrent Computer for Solving Systems of Linear Equations. 204-211.

Wolfe, A.; Breternitz, J. M.; Stephens, C.; Ting, A. L.; Kirk, D. B.; Bianchini, J. R. P.; Shen, J. P.: The White Dwarf: A High-Performance Application-Specific Processor. 212-222.

Gaudiot, J. L.; Lin, C. M.; Hosseiniyar, M.: Solving Partial Differential Equations in a Data-Driven Multiprocessor Environment. 223-231.

Lee, D.: Scrambled Storage for Parallel Memory Systems. 232-239.

Krishnaswamy, V.; Ahuja, S.; Carriero, N.; Gelernter, D.: The Architecture of a Linda Coprocessor. 240-251.

Kung, H. T.: Deadlock Avoidance for Systolic Communication. 252-260.

So, K.; Zecca, V.: Cache Performance of Vector Processors. 261-268.

Vernon, M. K.; Manber, U.: Distributed Round-Robin and First-Come First-Serve Protocols and Their Application to Multiprocessor Bus Arbitration. 269-279.

Agarwal, A.; Simoni, R.; Hennessy, J.; Horowitz, M.: An Evaluation of Directory Schemes for Cache Coherence. 280-289.

Przybylski, S.; Horowitz, M.; Hennessy, J.: Performance Tradeoffs in Cache Design. 290-298.

Cheong, H.; Veidenbaum, A. V.: A Cache Coherence Scheme with Fast Selective Invalidation. 299-307.

Vernon, M. K.; Lazowska, E. D.; Zahorjan, J.: An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols. 308-317.

Rau, D.; Fortes, J. A. B.; Siegel, H. J.: Destination Tag Routing Techniques Based on a State Model for the IADM Network. 318-324.

Kim, D. W.; Lipovski, G. J.; Hartmann, A.; Jenevein, R.: Regular CC-Banyan Networks. 325-332.

Jenevein, R. M; Mookken, T.: Traffic Analysis of Rectangular SW-Banyan Networks. 333-342.

Tamir, Y.; Frazier, G. L.: High-Performance Multi-Queue Buffers for VLSI Communication Switches. 343-355.

Giles, C. L.: Future Technologies Panel. 356-357.

Preiss, B. R.; Hamacher, V. C.: A Cache-Based Message Passing Scheme for a Shared-Bus Multiprocessor. 358-364.

Boku, T.; Nomura, S.; Amano, H.: IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation. 365-372.

Eggers, S. J.; Katz, R. H.: A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation. 373-383.

Lipovski, G. J.; Vaughan, P.: A Fetch-and-Op Implementation for Parallel Compiiters. 384-392.

Seznec, A.; Jégou, Y.: Synchronizing Processors through Memory Requests in a Tightly Coupled Multiprocessor. 393-400.

Fujimoto, R. M.; Tsai, J.-J.; Gopalakrishnan, G.: Design and Performance of Special Purpose Hardware for Time Warp. 401-409.

Cheriton, D. R.; Gupta, A.; Boyle, P. D.; Goosen, H. A.: The VMP Multiprocessor: Initial Experience, Refinements, and Performance Evaluation. 410-421.

Goodman, J. R.; Woest, P. J.: The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor. 422-433.

Tick, E.: Data Buffer Performance for Sequential Prolog Architectures. 434-442.

Halstead Jr., R. H.; Fujita, T.: MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing. 443-451.

Butler, P. L.; Allen, J. J. D.; Bouldin, D. W.: Parallel Architecture for OPS5. 452-459.

van Tilbourg, A. M.: Future Directions in Parallel Computer Architecture. 460-460.