ISCA91: Table of contents

DeMara, R. F.; Moldovan, D. I.: The SNAP-1 Parallel AI Prototype. 2-11.

Tan, W. S.; Russ, S. H.; Alford, C. O.: GT-EP: A Novel High-Performance Real-Time Architecture. 12-21.

Higuchi, T.; Furuya, T.; Handa, K.; Takahashi, N.; Nishiyama, H.; Kokubu, A.: IXM2: A Parallel Associative Processor. 22-33.

Kaeli, D. R.; Emma, P. G.: Branch History Table Prediction of Moving Target Branches Due to Subroutine Returns. 34-42.

Klaiber, A. C.; Levy, H. M.: An Architecture for Software-Controlled Data Prefetching. 43-53.

Fu, J. W. C.; Patel, J. H.: Data Prefetching in Multiprocessor Vector Cache Memories. 54-65.

Harper III, D. T.: Reducing Memory Contention in Shared Memory Multiprocessors. 66-73.

Rau, B. R.: Pseudo-Randomly Interleaved Memory. 74-83.

Li, K.; Petersen, K.: Evaluation of Memory System Extensions. 84-95.

Dowd, P. W.: High Performance Interprocessor Communication Through Optical Wavelength Division Multiple Access Channels. 96-105.

Landin, A.; Hagersten, E.; Haridi, S.: Race-free Interconnection Networks and Multiprocessor Consistency. 106-115.

Lin, X.; Ni, L. M.: Deadlock-Free Multicast Wormhole Routing in Multicomputer Networks. 116-127.

Farrens, M.; Park, A.: Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. 128-137.

Olukotun, O. A.; Mudge, T. N.; Brown, R. B.: Implementing a Cache for a High-Performance GaAs Microprocessor. 138-149.

Kurian, L.; Hulina, P. T.; Coraor, L. D.; Mannai, D. N.: Classification and Performance Evaluation of Instruction Buffering Techniques. 150-159.

Nakajima, M.; Nakano, H.; Nakakura, Y.; Yoshida, T.; Goi, Y.; Nakai, Y.; Segawa, R.; Kishida, T.; Kadota, H.: OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications. 160-169.

Vajapeyam, S.; Sohi, G. S.; Hsu, W.-C.: An Empirical Study of the CRAY Y-MP Processor using the PERFECT Club Benchmarks. 170-179.

Stephens, C.; Cogswell, B.; Heinlein, J.; Palmer, G.; Shen, J. P.: Instruction Level Profiling and Evaluation of the IBM RS/6000. 180-189.

Dimpsey, R. T.; Iyer, R. K.: Performance Prediction and Tuning on a Multiprocessor. 190-201.

Oehlrich, C.-W.; Quick, A.: Performance Evaluation of a Communication System for Transputer-Networks Based on Monitored Event Traces. 202-211.

Konstantinidou, S.; Snyder, L.: Chaos router: architecture and performance. 212-221.

Shukla, S. B.; Agrawal, D. P.: Scheduling Pipelined Communication in Distributed Memory Multiprocessors for Real-Time Applications. 222-233.

v. Adve, S.; Hill, M. D.; Miller, B. P.; Netzer, R. H. B.: Detecting Data Races on Weak Memory Systems. 234-243.

Koldinger, E. J.; Eggers, S. J.; Levy, H. M.: On the Validity of Trace-Driven Simulation for Multiprocessors. 244-253.

Gupta, A.; Hennessy, J.; Gharachorloo, K.; Mowry, T.; Weber, W.-D.: Comparative Evaluation of Latency Reducing and Tolerating Techniques. 254-265.

Chang, P. P.; Mahlke, S. A.; Chen, W. Y.; Warter, N. J.; Hwu, W. W.: IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. 266-275.

Butler, M.; Yeh, T.-Y.; Patt, Y.; Alsup, M.; Scales, H.; Shebanow, M.: Single Instruction Stream Parallelism Is Greater than Two. 276-286.

Melvin, S.; Patt, Y.: Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques. 287-297.

Adve, S. V.; Adve, V. S.; Hill, M. D.; Vernon, M. K.: Comparison of Hardware and Software Cache Coherence Schemes. 298-308.

Simoni, R.; Horowitz, M.: Modeling the Performance of Limited Pointers Directories for Cache Coherence. 309-319.

Quammen, D. J.; Miller, D. R.: Flexible Register Management for Sequential Programs. 320-329.

Bradlee, D. G.; Eggers, S. J.; Henry, R. R.: The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy. 330-341.

Papadopoulos, G. M.; Traub, K. R.: Multithreading: A Revisionist View of Dataflow Architectures. 342-351.

Chiueh, T.: Multi-Threaded Vectorization. 352-361.

Farrens, M. K.; Pleszkun, A. R.: Strategies for Achieving Improved Processor Throughput. 362-371.

Kagimasa, T.; Takahashi, K.; Mori, T.; Yoshizumi, S.: Adaptive Storage Management for Very Large Virtual/Real Storage Systems. 372-379.

Hall, J. S.; Robinson, P. T.: Virtualizing the VAX Architecture. 380-389.

Akella, J.; Siewiorek, D. P.: Modeling and Measurement of the Impact of Input/Output on System Performance. 390-399.