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Note: Links lead to the DBLP on the Web. Klaus Schneider 28 Klaus Schneider: Proving the Equivalence of Microstep and Macrostep Semantics. TPHOLs 2002 : 314-331 27 Klaus Schneider: Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy. LPAR 2001 : 39-54 26 George Logothetis , Klaus Schneider: Symbolic Model Checking of Real-Time Systems. TIME 2001 : 214-223 25 Klaus Schneider: A Verified Hardware Synthesis of Esterel Programs. DIPES 2000 : 205-214 24 Klaus Schneider: Yet another Look at the LTL Model Checking. CHARME 1999 : 321-325 23 Klaus Schneider, Michaela Huhn , George Logothetis : Validation of Object-Oriented Concurrent Designs by Model Checking. CHARME 1999 : 360-364 22 Klaus Schneider, Viktor K. Sabelfeld : Introducing Mutual Exclusion in Esterel. Ershov Memorial Conference 1999 : 445-459 21 Klaus Schneider, Dirk W. Hoffmann : A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata. TPHOLs 1999 : 255-272 20 Klaus Schneider: Model Checking on Product Structures. FMCAD 1998 : 483-500 19 Klaus Schneider, Thomas Kropf : The C@S System. Formal Hardware Verification 1997 : 248-329 18 Klaus Schneider, Thomas Kropf : A Unified Approach for Combining Different Formalisms for Hardware Verification. FMCAD 1996 : 202-217 17 Klaus Schneider, Thomas Kropf , Ramayya Kumar : Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. EDAC-ETC-EUROASIC 1994 : 648-652 16 Thomas Kropf , Klaus Schneider, Ramayya Kumar : A Formal Framework for High Level Synthesis. TPCD 1994 : 223-238 15 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Automating Verification by Functional Abstraction at the System Level. TPHOLs 1994 : 391-406 14 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Accelerating Tableaux Proofs Using Compact Representations. Formal Methods in System Design 5 (1/2): 145-176 (1994) 13 Thomas Kropf , Ramayya Kumar , Klaus Schneider: Embedding Hardware Verification Within a Commercial Design Framework. CHARME 1993 : 242-257 12 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Hardware-Verification using First Order BDDs. CHDL 1993 : 45-62 11 Dirk Eisenbiegler , Klaus Schneider, Ramayya Kumar : A Functional Approach for Formalizing Regular Hardware Structures. HUG 1993 : 101-114 10 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. HUG 1993 : 213-226 9 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. HUG 1993 : 385-398 8 Ramayya Kumar , Klaus Schneider, Thomas Kropf : Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. Formal Methods in System Design 2 (2): 165-223 (1993) 7 Klaus Schneider, Ramayya Kumar , Thomas Kropf : The FAUST - Prover. CADE 1992 : 766-770 6 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Modelling Generic Hardware Structures by Abstract Datatypes. TPHOLs 1992 : 165-175 5 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Efficient Representation and Computation of Tableau Proofs. TPHOLs 1992 : 39-57 4 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Automating Most Parts of Hardware Proofs in HOL. CAV 1991 : 365-375 3 Ramayya Kumar , Thomas Kropf , Klaus Schneider: Integrating a First-Order Automatic Prover in the HOL Environment. TPHOLs 1991 : 170-176 2 Ramayya Kumar , Thomas Kropf , Klaus Schneider: First Steps Towards Automating Hardware Proofs in HOL. TPHOLs 1991 : 190-193 1 Klaus Schneider, Ramayya Kumar , Thomas Kropf : Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment. VLSI 1991 : 81-90  DiSC'02 © 2003 Association for Computing Machinery |
