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Note: Links lead to the DBLP on the Web. Daehyun Kim Taeweon Suh , Daehyun Kim, Hsien-Hsin S. Lee : Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. DAC 2005 : 553-558 Amol Ghoting , Gregory Buehrer , Srinivasan Parthasarathy , Daehyun Kim, Anthony Nguyen , Yen-Kuang Chen , Pradeep Dubey : A Characterization of Data Mining Workloads on a Modern Processor. DaMoN 2005 Amol Ghoting , Gregory Buehrer , Srinivasan Parthasarathy , Daehyun Kim, Anthony Nguyen , Yen-Kuang Chen , Pradeep Dubey : Cache-conscious Frequent Pattern Mining on a Modern Processor. VLDB 2005 : 577-588 Daehyun Kim, Mainak Chaudhuri , Mark Heinrich , Evan Speight : Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems. IEEE Trans. Computers 53 (3): 288-307 (2004) Daehyun Kim, Mainak Chaudhuri , Mark Heinrich : Active Memory Techniques for ccNUMA Multiprocessors. IPDPS 2003 : 10 Daehyun Kim, Mainak Chaudhuri , Mark Heinrich : Leveraging cache coherence in active memory systems. ICS 2002 : 2-13 Mainak Chaudhuri , Daehyun Kim, Mark Heinrich : Cache Coherence Protocol Design for Active Memory Systems. PDPTA 2002 : 83-89 1 [ 5 ] [ 6 ] 2 [ 1 ] [ 2 ] [ 3 ] [ 4 ] 3 [ 5 ] [ 6 ] 4 [ 5 ] [ 6 ] 5 [ 5 ] [ 6 ] 6 [ 1 ] [ 2 ] [ 3 ] [ 4 ] 7 [ 7 ] 8 [ 5 ] [ 6 ] 9 [ 5 ] [ 6 ] 10 [ 4 ] 11 [ 7 ]  ©2006 Association for Computing Machinery |
