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J. Gregory Steffan

Papers on DiSC'06


Optimistic Intra-Transaction Parallelism on Chip Multiprocessors

Publications


Note: Links lead to the DBLP on the Web.

J. Gregory Steffan

Peter Yiannacouras , J. Gregory Steffan, Jonathan Rose : Application-specific customization of soft processor microarchitecture. FPGA 2006 : 201-210

Peter Yiannacouras , Jonathan Rose , J. Gregory Steffan: The microarchitecture of FPGA-based soft processors. CASES 2005 : 202-212

Christopher B. Colohan , Anastassia Ailamaki , J. Gregory Steffan, Todd C. Mowry : Optimistic Intra-Transaction Parallelism on Chip Multiprocessors. VLDB 2005 : 73-84

J. Gregory Steffan, Christopher B. Colohan , Antonia Zhai , Todd C. Mowry : The STAMPede approach to thread-level speculation. ACM Trans. Comput. Syst. 23 (3): 253-300 (2005)

Antonia Zhai , Christopher B. Colohan , J. Gregory Steffan, Todd C. Mowry : Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads. CGO 2004 : 39-52

Antonia Zhai , Christopher B. Colohan , J. Gregory Steffan, Todd C. Mowry : Compiler optimization of scalar value communication between speculative threads. ASPLOS 2002 : 171-183

J. Gregory Steffan, Christopher B. Colohan , Antonia Zhai , Todd C. Mowry : Improving Value Communication for Thread-Level Speculation. HPCA 2002 : 65-

J. Gregory Steffan, Christopher B. Colohan , Antonia Zhai , Todd C. Mowry : A scalable approach to thread-level speculation. ISCA 2000 : 1-12

J. Gregory Steffan, Todd C. Mowry : The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization. HPCA 1998 : 2-13

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